Dao Van Lan, Nguyen Anh Thai, Hoang Van Phuc

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This paper presents a low area, low power AES-CCM authenticated encryption IP core with silicon demonstration in 180nm standard CMOS process. The proposed AES-CCM core combines a low area 8-bit single S-box AES encryption core, improved iterative structure and other optimized circuits. The implementation results show that the proposed AES-CCM core achieves very high resource efficiency with 6.5 kgates GE and the low power consumption of 11.6 µW/MHz while meeting the requirement of the operation speed for many applications including IEEE 802.15.6 WBANs. The detail implementation and optimization results are also presented and discussed.